1. Technical Field of the Invention
This invention pertains to testing electronic memory. In particular, this invention describes a method and apparatus for testing and diagnosing RAM failures on the fly and for providing fast and reliable information about individual RAM defects.
2. Background Art
RAM testing is a process of exercising RAM and determining whether or not the memory behaves correctly. If the memory misbehaves, diagnosis is performed on the memory to determine the cause of the misbehavior. As the complexity of microprocessors continues to increase, so, too, does the importance of memory test and diagnosis. During manufacturing test is the most important component because bad memory chips need to be identified and discarded. The second important step, diagnosis, becomes crucial when the yield is low and it becomes necessary to pinpoint the defects or family of defects that are bringing down the yield.
The invention described herein involves the test and diagnosis of memory arrays embedded in a large microprocessor, for example, a translation look-aside buffer. Larger memory arrays on the processor chip are tested using built-in self-test (BIST). However, the number and size of smaller arrays does not warrant the design time nor the chip space to test them using BIST. The approach to testing smaller arrays is to use functional patterns, whereby the pins of the chip are driven with stimuli and then observed for responses while the chip is operating in functional mode, i.e. as it would normally operate. Essentially, the test algorithm is run on the chip in the form of a working program.
The present invention is directed to a test strategy, method, and apparatus that is based on functional test patterns. In general, functional patterns require too much time due to the demands of pattern generation and fault simulation. However, these shortcomings are surmountable for the case of memory array testing and diagnosis. For memory arrays, pattern generation is not as much of a problem because memory is structurally very regular, and fault simulation is not required. For normal array tests it is known what defects, and what combination of defects, are covered. Finally, the use of functional patterns makes it possible to use to on-chip caching mechanisms to reduce the actual number of test vectors that have to be stored in the test buffer.
Using functional patterns does complicate the diagnosis however, although not more so than using BIST. The main problem is that the tester is a passive supplier of clock signals and input stimuli, and is not involved in interpreting the observed fail data beyond merely recording them. In order to do diagnosis, however, information on which bits in the RAM are failing and what phase of the test made that observation has to be recorded. The information on the phase of the test can be reconstructed, of course, from the vector number, but that is an awkward, and rather inflexible, approach.
The present invention provides, first, an accurate diagnosis within a given granularity of a diagnostic procedure (given the set of tests that were employed) and, second, achieving that level of granularity in an acceptable way, that is, without extensive post test analysis and simulation. An additional, and equally important, provision is a reduction of tester buffer requirements, simulation, and test vector generation turn-around times, etc., without compromising the optimum potential granularity.
It is an object of the invention to provide an improved methodology for memory array diagnosis.
It is another object of the invention to provide an article of manufacture for implementing an improved test and diagnosis methodology for memory arrays.
The present invention is directed to a test strategy that is 1) based on functional patterns, and 2) allows for easy diagnosis, with the emphasis on diagnosis and not so much on test. Therefore, the description of which tests catch the faults is not directed towards the most efficient tests, but to tests that allow for diagnosis. The requirement of easy diagnosibility led to several novel advancements and to novel accommodations as to how the tests can be modified to alleviate pattern generation and simulation bottlenecks.
Briefly, the diagnostic flow proceeds as follows: first, test patterns are generated. These patterns are applied by the tester to the chip being tested. The tester continues applying the patterns, collecting fail data, if any, in the process. Unlike go/no-go testing, the tester does not stop on first exposure. The resulting tester output is then analyzed to generate a failure bitmap. By applying the criteria described in detail below, a final diagnosis can be made.
The goal of easy and full diagnosibility does not require tests in which the processor itself is involved in detecting faults. It also restricts the kind of optimizations that can be performed to reduce the tester time, the required tester buffer size, and the simulation turnaround time.
Other features and advantages of this invention will become apparent from the following detailed description of the presently preferred embodiment of the invention, taken in conjunction with the accompanying drawings.
FIG. 1 illustrates a generic memory array architecture.
FIGS. 2A-2B illustrate examples of non-deterministic faults.
FIGS. 3A-3B illustrate examples of linked faults.
FIG. 4 illustrates an example of a state-coupling fault.
FIG. 5 illustrates an example of a read/write logic fault.
FIGS. 6a-d illustrate examples of logical address decoder faults.
FIG. 7 illustrates a range of possible scopes of different faults.
FIG. 8 illustrates a sample memory.
FIG. 9 illustrates information encoding using the present inventive method suitable for diagnosis.
FIGS. 10a-b illustrate components for catching coupling faults.
FIGS. 11a-d illustrate fault signatures of idempotent faults.
FIGS. 12a-c illustrate fault signatures of inversion faults.
FIGS. 13a-b illustrate fault signatures of state-coupling faults.
FIG. 14 illustrates an addressing clarification.
FIGS. 15-17 illustrate fault signatures of row decoder faults.
FIG. 18 illustrates breaking up the unique address ripple word test.
FIG. 19 illustrates preserving coupling faults.
FIG. 20 illustrates catching a row decoder fault.
FIG. 21 illustrates catching a column decoder fault.
FIG. 22 illustrates an overall flowchart of the present inventive method.